디노티시아

Roles and ​Responsibilities

· Verification ​planning ​and testbench ​architecturing

· Write testplan from design ​specification

​ ​ - Description ​of directed ​and ​constraint random ​tests

​ ​ - ​Description ​of functional coverage ​(cover ​points)

​ ​- Description of ​scoreboard ​and assertions ​

· Implement UVM ​testbench ​and tests

· Implement reusable ​and consistent ​test environment

· Verification signoff

- Meet code/functional coverage target

- Write signoff checklist

· DV infrastructure and methodology

- Automation of infrastructure and DV methodology

- Implement in-house VIP

- Apply advanced verification methodology

Basic Qualifications

· Deep knowledge of SystemVerilog and UVM.

· Experience developing UVM based testbenches

· Experience with complex designs and advanced debug skills ability

· Strong communication skills and interface with a lot of different groups within

the company and partners.

Preferred Qualifications

· Experience in formal verification

· Experience in design verification modeling (C++, System C)

· Experience in serial/parallel protocols such as Memory, PCIe and UCIe