Roles and Responsibilities
· Design, develop, and optimize RTL components for high performance and low power consumption
using Verilog.
· Collaborate with cross-functional teams to define chip architecture and module specifications.
· Lead the integration of various IP blocks and ensure compliance with overall architectural requirements.
· Conduct synthesis, timing analysis, and power optimization to meet design goals.
· Work closely with the verification team to define verification plans and ensure design robustness.
· Implement debugging methodologies at both the unit and system levels.
· Support synthesis, timing analysis, and DFT (Design for Testability) requirements for SoC designs.
· Participate in design reviews, contribute to documentation, and ensure the delivery of high-quality
deliverables
· Stay updated on industry trends and technologies to drive innovation within the company.
Basic Qualifications
· Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
· A minimum of 3-7+ years of experience in RTL design and SoC development.
· Extensive knowledge and hands-on experience in computer architecture.
· Solid understanding of CPU, GPU, and NPU architectures, including pipelines, caches,
and memory systems.
· Expertise in Verilog or VHDL, with a strong understanding of ASIC and FPGA design processes.
· Familiarity with EDA tools such as Cadence, Synopsys, or Mentor Graphics.
· Strong problem-solving abilities and excellent communication skills.
Preferred Qualifications
· Experience with low-power design techniques and methodologies.
· Familiarity with scripting languages such as Python or Tcl.
· Knowledge of hardware/software co-design and debugging.
Tools and Technologies
· RTL Design: Verilog, SystemVerilog
· Synthesis and Timing: Synopsys DC, Cadence Genus, PrimeTime
· Simulation and Debugging: ModelSim, VCS, DVE
· Protocols: AMBA (AXI, AHB, APB), PCIe, UCIe, etc.
· Version Control: Git, Perforce
Roles and Responsibilities
· Design, develop, and optimize RTL components for high performance and low power consumption
using Verilog.
· Collaborate with cross-functional teams to define chip architecture and module specifications.
· Lead the integration of various IP blocks and ensure compliance with overall architectural requirements.
· Conduct synthesis, timing analysis, and power optimization to meet design goals.
· Work closely with the verification team to define verification plans and ensure design robustness.
· Implement debugging methodologies at both the unit and system levels.
· Support synthesis, timing analysis, and DFT (Design for Testability) requirements for SoC designs.
· Participate in design reviews, contribute to documentation, and ensure the delivery of high-quality
deliverables
· Stay updated on industry trends and technologies to drive innovation within the company.
Basic Qualifications
· Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
· A minimum of 3-7+ years of experience in RTL design and SoC development.
· Extensive knowledge and hands-on experience in computer architecture.
· Solid understanding of CPU, GPU, and NPU architectures, including pipelines, caches,
and memory systems.
· Expertise in Verilog or VHDL, with a strong understanding of ASIC and FPGA design processes.
· Familiarity with EDA tools such as Cadence, Synopsys, or Mentor Graphics.
· Strong problem-solving abilities and excellent communication skills.
Preferred Qualifications
· Experience with low-power design techniques and methodologies.
· Familiarity with scripting languages such as Python or Tcl.
· Knowledge of hardware/software co-design and debugging.
Tools and Technologies
· RTL Design: Verilog, SystemVerilog
· Synthesis and Timing: Synopsys DC, Cadence Genus, PrimeTime
· Simulation and Debugging: ModelSim, VCS, DVE
· Protocols: AMBA (AXI, AHB, APB), PCIe, UCIe, etc.
· Version Control: Git, Perforce