디노티시아

Roles and ​Responsibilities

· Design, ​develop, ​and optimize ​RTL components for high ​performance ​and low ​power consumption

​ using ​Verilog.

· Collaborate ​with cross-functional ​teams ​to ​define chip architecture ​and ​module specifications.

· Lead the ​integration ​of ​various IP blocks ​and ensure ​compliance ​with overall ​architectural requirements.

· Conduct ​synthesis, ​timing analysis, and ​power optimization ​to meet design goals.

· Work closely with the verification team to define verification plans and ensure design robustness.

· Implement debugging methodologies at both the unit and system levels.

Basic Qualifications

· Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

· A minimum of 4 years of experience in RTL design and SoC development.

· Extensive knowledge and hands-on experience in computer architecture.

· Expertise in Verilog with a strong understanding of ASIC and FPGA design processes.

· Familiarity with EDA tools such as Cadence, Synopsys, or Mentor Graphics.

· Strong problem-solving abilities and excellent communication skills.

Preferred Qualifications

· Experience with low-power design techniques and methodologies.

· Familiarity with scripting languages such as Python or Tcl.

· Proven track record in designing and launching mass production chips.